1. Field of the Invention
The present invention relates to a power-up reset circuit, and more particularly to a power-up reset circuit configured to make a reset signal insensible to variations of a power-up slope and a temperature, thereby improving stability of operations.
2. Description of the Background Art
In general, a ferroelectric random access memory (FeRAM) has a data processing speed equivalent to a dynamic random access memory (DRAM), and preserves data even when power is off.
The FeRAM is a memory having a similar tructure to the DRAM. The FeRAM employs a ferroelectric substance to form capacitors, and thus uses high remanent polarization which is a property of the ferroelectric substance. Even if electric fields are removed, data are not deleted in the FeRAM due to the remanent polarization.
The technical descriptions of the FeRAM have been disclosed in Korea Patent application No. 1998-14400 by the same inventors as the present invention. Therefore, detailed explanations of the basic structures and operation principles of the FeRAM are omitted.
In a system using the FeRAM as a memory element, when a system controller outputs a chip enable signal to an FeRAM chip, a memory of the FeRAM chip generates a chip internal control signal for operating a memory cell of the chip according to the chip enable signal. Data are recorded on the memory cell or read according to the chip internal control signal.
When power is initially supplied to the FeRAM, the system using the FeRAM must be reset by reading data stored in a code register. The read operation in the code register is performed by using a power-up reset signal.
In a conventional reset circuit, a power-up slope of voltage considerably influences generation of a reset signal. Therefore, when power gradually increases (when the power-up slope is small), the reset signal is generated even in a lower power voltage than a reference voltage.
FIG. 1 is a circuit diagram illustrating the conventional reset circuit.
Referring to FIG. 1, the reset circuit includes a PMOS transistor T1 having its gate terminal connected to a ground voltage terminal VSS, and an NMOS transistor T2 having its gate terminal connected to receive the output from the PMOS transistor T1, and its drain and source terminals commonly connected to the ground voltage terminal VSS. In addition, the reset circuit includes chained inverters INV1, INV2 and INV3 for sequentially inverting the output from the PMOS transistor T1, and a PMOS transistor T3 composing a latch with the inverter INV2.
A slope of the output signal RESET from the reset circuit is decided according to an RC delay time between the PMOS transistor T1 which is a pull-up current source having a channel resistance and the NMOS transistor T2 operating as a capacitor.
Accordingly, the power-up operation must be performed within a predetermined time to stably operate a memory chip. If the power-up time exceeds the predetermined time due to some factors generated in the code register, the data stored in the code register are destroyed.
FIGS. 2 and 3 are timing diagrams showing generation of the reset signal when the power voltage increases on a fast slope and a slow slope, respectively.
As illustrated in FIG. 2, when the power voltage rises from the ground voltage level VSS to the power voltage level Vcc on a fast slope, the reset signal is generated over a predetermined voltage. Conversely, as shown in FIG. 3, when the power voltage gradually rises from the ground voltage level VSS to the power voltage level Vcc on a slow slope, the NMOS transistor T2 is precharged for a longer time than FIG. 2, a sensing level of the NMOS transistor T2 is rapidly heightened, and thus the reset signal is generated in a low voltage.
As mentioned above, when generation of the reset signal is destabilized according to variations of the power voltage, the code register may be operated in a lower voltage than a normal voltage. When the code register is operated in a too low voltage, the data stored in the code register are mistakenly read or unstably restored, to cause failures in operations of the code register.
Moreover, properties of a semiconductor device are changed due to variations of a temperature, which destabilizes generation of the reset signal.
FIG. 4 is a diagram illustrating temperature properties of an NMOS/PMOS transistor.
As depicted in FIG. 4, when a temperature rises, a threshold voltage Vtn(-Vtp) of the NMOS/PMOS transistor decreases. As a result, the transistors are turned on even in a low power voltage, to generate the reset signal.